High-speed serial I/O is a critical part of computing systems. In server applications where I/O number in the thousands, achieving low-power and low-area I/O circuitry is paramount. It is common for receivers to be calibrated (i.e., determine sampling clock phase, equalizer coefficients, offset settings, etc) at startup; however, failure to recalibrate during normal receiver operation makes the links susceptible to temperature drifts. Redundant hardware can be employed to enable continuous link recalibration without interrupting data transmission. For example, at the bit receiver level additional parallel paths can be included to enable eye monitoring capabilities or edge sampling for timing recovery. These paths are included in parallel with a data sampling path which processes data in an uninterrupted fashion. This level of redundancy results in at least 100% hardware overhead. To reduce the overhead in a parallel interface, redundant lanes can be included. This approach includes at least one additional transmitter, channel, and receiver within an N-wide parallel interface. N+1 lanes can be included such that N lanes are available for continuous data communication, while the extra lane permits recalibration of all lanes in a “round-robin” fashion. Either approach results in higher power consumption due to the extra circuitry involved. The latter approach also requires additional C4 pins in a parallel interface to enable the extra lane. Moreover, protocol overhead is required to schedule which lane is being recalibrated, and which of the N lanes contain information about the data that is being communicated.
It would be highly desirable to employ bus-level redundancy only within the receiver of a parallel interface to permit periodic recalibration of all receivers. This avoids the 100% overhead associated with bit-receiver level redundancy. Moreover, it avoids the transmit and lane overhead at the bus level associated with lane redundancy.